The speed of an FET is largely determined by the distance across the gate; transistors with a shorter gate conductor distance have a shorter spacing between source and drain and are generally faster. The industry has moved to photolithography equipment that provides a shorter wavelength of light and a higher numerical aperture lens with each generation of integrated circuits to permit decreasing this dimension of the gate. However, these changes have frequently increased cross chip line width variation. Furthermore, these changes have resulted in higher gate resistance.
U.S. Pat. No. 5,750,430, to Jeong-Hwan Son describes a gate having curved sidewalls produced by depositing polysilicon for the gate in a window between spacers. The transistor has a larger dimension at the top than at the bottom. It provides a channel length that is shorter than the minimum dimension and reduced overlap capacitance. An FET with a notch at the bottom of the poly gate was described in a paper “100 nm Gate Length High performance/Low Power CMOS Transistor,” by T. Ghani et al, Technical Digest of the 1999 International Electron Devices Meeting, Washington, D.C., 1999, p 415. The notch offsets the source-drain-extension implant and provides a shorter gate dimension with improved capacitance and also avoids increasing resistance since the gate has a larger overall cross sectional area.
The spacer defined gate with the curved sidewalls and the notched gate provide advantage but substantial further device performance improvement is possible. This improvement may be derived by modifying the structures described in the '430 patent and the paper by T. Ghani. The new structures and processes to achieve those new structures are provided by the following invention.